Tutorial by Examples

Simple Dual Port RAM with separate addresses and clocks for read/write operations. module simple_ram_dual_clock #( parameter DATA_WIDTH=8, //width of data bus parameter ADDR_WIDTH=8 //width of addresses buses )( input [DATA_WIDTH-1:0] data, //da...

Simple Single Port RAM with one address for read/write operations. module ram_single #( parameter DATA_WIDTH=8, //width of data bus parameter ADDR_WIDTH=8 //width of addresses buses )( input [(DATA_WIDTH-1):0] data, //data to be written input [(ADDR_WIDTH-1):0] ad...

N-bit deep shift register with asynchronous reset. module shift_register #( parameter REG_DEPTH = 16 )( input clk, //clock signal input ena, //enable signal input rst, //reset signal input data_in, //input bit output data_out //output bit ); reg [REG_DE...

Simple single port RAM with async read/write operations module ram_single_port_ar_aw #( parameter DATA_WIDTH = 8, parameter ADDR_WITDH = 3 )( input we, // write enable input oe, // output enable input [(ADDR_WITDH-1):0] waddr, // ...