Tutorial by Examples

A VHDL program can be simulated or synthesized. Simulation is what resembles most the execution in other programming languages. Synthesis translates a VHDL program into a network of logic gates. Many VHDL simulation and synthesis tools are parts of commercial Electronic Design Automation (EDA) s...

-- File counter.vhd -- The entity is the interface part. It has a name and a set of input / output -- ports. Ports have a name, a direction and a type. The bit type has only two -- values: '0' and '1'. It is one of the standard types. entity counter is port( clock: in bit; -- We ...

There are many ways to print the classical "Hello world!" message in VHDL. The simplest of all is probably something like: -- File hello_world.vhd entity hello_world is end entity hello_world; architecture arc of hello_world is begin assert false report "Hello world!&quo...

Simulation environments A simulation environment for a VHDL design (the Design Under Test or DUT) is another VHDL design that, at a minimum: Declares signals corresponding to the input and output ports of the DUT. Instantiates the DUT and connects its ports to the declared signals. Instant...

This example deals with one of the most fundamental aspects of the VHDL language: the simulation semantics. It is intended for VHDL beginners and presents a simplified view where many details have been omitted (postponed processes, VHDL Procedural Interface, shared variables...) Readers interest...