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A shift register of generic length. With serial in and serial out. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity SHIFT_REG is generic( LENGTH: natural := 8 ); port( SHIFT_EN : in std_logic; SO : out std_logic; ...

ROM

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity ROM is port( address : in std_logic_vector(3 downto 0); dout : out std_logic_vector(3 downto 0) ); end entity ROM; architecture RTL of ROM is type MEMORY_16_4 is array (0 to 15) ...
Last In First Out (Stack) Memory library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity LIFO is generic( WIDTH : natural := 8; DEPTH : natural := 128 ); port( I_DATA : in std_logic_vector(WIDTH - 1 downto 0); --Input Data Line ...

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