Example
Within the context of an individual rule, Make automatically defines a number of special variables. These variables can have a different value for each rule in a makefile and are designed to make writing rules simpler. These variables can only be used in the recipe portion of a rule.
| Variable | Description |
|---|---|
$@ | File name of the rule's target |
$% | The target member's name, if the rule's target is an archive |
$< | File name of the first prerequisite |
$^ | List of all prerequisites |
$? | List of all prerequisites that are newer than the target |
$* | The "stem" of an implicit or pattern rule |
The following example uses automatic variables to generate a generic rule. This instructs make how to construct a .o file out of a .c file with the same name. Since we don't know the specific name of the affected files, we use $@ as a placeholder for the output file's name and $^ as a placeholder for the prerequisite list (in this case, the list of input files).
%.o: %.c
cc -Wall $^ -c $@
