verilog Memories Shift register

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Example

N-bit deep shift register with asynchronous reset.

module shift_register #(
  parameter REG_DEPTH = 16
)(
  input clk,       //clock signal
  input ena,       //enable signal
  input rst,       //reset signal
  input data_in,   //input bit
  output data_out  //output bit
);

  reg [REG_DEPTH-1:0] data_reg;

  always @(posedge clk or posedge rst) begin
    if (rst) begin //asynchronous reset
      data_reg <= {REG_DEPTH{1'b0}}; //load REG_DEPTH zeros
    end else if (enable) begin
      data_reg <= {data_reg[REG_DEPTH-2:0], data_in}; //load input data as LSB and shift (left) all other bits 
    end
  end

  assign data_out = data_reg[REG_DEPTH-1]; //MSB is an output bit

endmodule


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