verilog Getting started with verilog Hello World

Example

This example uses the icarus verilog compiler.

Step 1: Create a file called hello.v

module myModule();

initial
  begin
    $display("Hello World!");   // This will display a message
    $finish ; // This causes the simulation to end.  Without, it would go on..and on.
  end

endmodule

Step 2. We compile the .v file using icarus:

>iverilog -o hello.vvp hello.v

The -o switch assigns a name to the output object file. Without this switch the output file would be called a.out. The hello.v indicates the source file to be compiled. There should be practically no output when you compile this source code, unless there are errors.

Step 3. You are ready to simulate this Hello World verilog program. To do so, invoke as such:

>vvp hello.vvp 
Hello World!
>