Tutorial by Examples

A counter using an FPGA style flip-flop initialisation: module counter( input clk, output reg[7:0] count ) initial count = 0; always @ (posedge clk) begin count <= count + 1'b1; end A counter implemented using asynchronous resets suitable for ASIC synthesis: module counter...

A non-blocking assignment (<=) is used for assignment inside edge-sensitive always blocks. Within a block, the new values are not visible until the entire block has been processed. For example: module flip( input clk, input reset ) reg f1; reg f2; always @ (posedge clk) begin ...