verilog Procedural Blocks Simple counter

Example

A counter using an FPGA style flip-flop initialisation:

module counter(
    input clk,
    output reg[7:0] count
)
initial count = 0;
always @ (posedge clk) begin
    count <= count + 1'b1;
end

A counter implemented using asynchronous resets suitable for ASIC synthesis:

module counter(
  input            clk,  
  input            rst_n, // Active-low reset
  output reg [7:0] count
)
always @ (posedge clk or negedge rst_n) begin
  if (~rst_n) begin
    count <= 'b0;
  end
  else begin
    count <= count + 1'b1;
  end
end

The procedural blocks in these examples increment count at every rising clock edge.