verilog Procedural Blocks Non-blocking assignments


A non-blocking assignment (<=) is used for assignment inside edge-sensitive always blocks. Within a block, the new values are not visible until the entire block has been processed. For example:

module flip(
    input clk,
    input reset
reg f1;
reg f2;

always @ (posedge clk) begin
  if (reset) begin // synchronous reset
    f1 <= 0;
    f2 <= 1;
  else begin
    f1 <= f2;
    f2 <= f1;

Notice the use of non-blocking (<=) assignments here. Since the first assignment doesn't actually take effect until after the procedural block, the second assignment does what is intended and actually swaps the two variables -- unlike in a blocking assignment (=) or assignments in other languages; f1 still has its original value on the right-hand-side of the second assignment in the block.