Tutorial by Examples

In all examples: clk is the clock, d is the input, q is the output, srst is an active high synchronous reset, srstn is an active low synchronous reset, arst is an active high asynchronous reset, arstn is an active low asynchronous reset, sset is an active high synchronous set, ssetn is an...

In all examples: en is the enable signal, d is the input, q is the output, srst is an active high synchronous reset, srstn is an active low synchronous reset, arst is an active high asynchronous reset, arstn is an active low asynchronous reset, sset is an active high synchronous set, sset...

The short story Whith VHDL 2008 and if the type of the clock is bit, boolean, ieee.std_logic_1164.std_ulogic or ieee.std_logic_1164.std_logic, a clock edge detection can be coded for rising edge if rising_edge(clock) then if clock'event and clock = '1' then -- type bit, std_ulogic or std_logic ...