vhdl D-Flip-Flops (DFF) and latches
Remarks
D-Flip-Flops (DFF) and latches are memory elements. A DFF samples its input on one or the other edge of its clock (not both) while a latch is transparent on one level of its enable and memorizing on the other. The following figure illustrates the difference:
Modelling DFFs or latches in VHDL is easy but there are a few important aspects that must be taken into account:
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The differences between VHDL models of DFFs and latches.
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How to describe the edges of a signal.
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How to describe synchronous or asynchronous set or resets.
