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vhdl
Getting started with vhdl
Comments
D-Flip-Flops (DFF) and latches
Digital hardware design using VHDL in a nutshell
Identifiers
Literals
Memories
Protected types
Recursivity
Resolution functions, unresolved and resolved types
Static Timing Analysis - what does it mean when a design fails timing?
Wait
Eternal wait
Sensitivity lists and wait statements
Wait for a specific duration
Wait until condition
vhdl
Getting started with vhdl
Comments
D-Flip-Flops (DFF) and latches
Digital hardware design using VHDL in a nutshell
Identifiers
Literals
Memories
Protected types
Recursivity
Resolution functions, unresolved and resolved types
Static Timing Analysis - what does it mean when a design fails timing?
Wait
Eternal wait
Sensitivity lists and wait statements
Wait for a specific duration
Wait until condition
vhdl
Wait
Syntax
wait [on SIGNAL1[, SIGNAL2[...]]] [until CONDITION] [for TIMEOUT];
wait; -- Eternal wait
wait on s1, s2; -- Wait until signals s1 or s2 (or both) change
wait until s1 = 15; -- Wait until signal s1 changes and its new value is 15
wait until s1 = 15 for 10 ns; -- Wait until signal s1 changes and its new value is 15 for at most 10 ns
Wait Related Examples
Eternal wait
Sensitivity lists and wait statements
Wait for a specific duration
Wait until condition
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