vhdl Eternal wait


Example

The simplest form of wait statement is simply:

wait;

Whenever a process executes this it is suspended forever. The simulation scheduler will never resume it again. Example:

signal end_of_simulation: boolean := false;
...
process
begin
  clock <= '0';
  wait for 500 ps;
  clock <= '1';
  wait for 500 ps;
  if end_of_simulation then
    wait;
  end if;
end process;