using only the
for <timeout> clause, it is possible to get an unconditional wait that lasts for a specific duration. This is not synthesizable (no real hardware can perform this behaviour so simply), but is frequently used for scheduling events and generating clocks within a testbench.
This example generates a 100 MHz, 50% duty cycle clock in the simulation testbench for driving the unit under test:
constant period : time := 10 ns; ... process begin loop clk <= '0'; wait for period/2; clk <= '1'; wait for period/2; end loop; end process;
This example demonstrates how one might use a literal duration wait to sequence the testbench stimulus/analysis process:
process begin rst <= '1'; wait for 50 ns; wait until rising_edge(clk); --deassert reset synchronously rst <= '0'; uut_input <= test_constant; wait for 100 us; --allow time for the uut to process the input if uut_output /= expected_output_constant then assert false report "failed test" severity error; else assert false report "passed first stage" severity note; uut_process_stage_2 <= '1'; end if; ... wait; end process;