vhdl Resolution functions, unresolved and resolved types
Introduction
VHDL types can be unresolved or resolved. The bit type declared by the std.standard package, for instance, is unresolved while the std_logic type declared by the ieee.std_logic_1164 package is resolved.
A signal which type is unresolved cannot be driven (assigned) by more than one VHDL process while a signal which type is resolved can.
Remarks
The use of resolved types should be reserved to situations where the intention is really to model a hardware wire (or set of wires) driven by more than one hardware circuit. A typical case where it is needed is the bi-directional data bus of a memory: when the memory is written it is the writing device that drives the bus while when the memory is read it is the memory that drives the bus.
Using resolved types in other situations, while a frequently encountered practice, is a bad idea because it suppresses very useful compilation errors when unwanted multiple drive situations are accidentally created.
The ieee.numeric_std package declares the signed and unsigned vector types and overloads the arithmetic operators on them. These types are frequently used when arithmetic and bit-wise operations are needed on the same data. The signed and unsigned types are resolved. Prior VHDL2008, using ieee.numeric_std and its types thus implied that accidental multiple drive situations would not raise compilation errors. VHDL2008 adds new type declarations to ieee.numeric_std: unresolved_signed and unresolved_unsigned (aliases u_signed and u_unsigned). These new types should be preferred in all cases where multiple drive situations are not desired.
