vhdl Resolution functions, unresolved and resolved types Two processes driving the same signal of type `bit`
Example
The following VHDL model drives signal s from two different processes. As the type of s is bit, an unresolved type, this is not allowed.
-- File md.vhd
entity md is
end entity md;
architecture arc of md is
signal s: bit;
begin
p1: process
begin
s <= '0';
wait;
end process p1;
p2: process
begin
s <= '0';
wait;
end process p2;
end architecture arc;
Compiling, elaborating and trying to simulate, e.g. with GHDL, raise an error:
ghdl -a md.vhd
ghdl -e md
./md
for signal: .md(arc).s
./md:error: several sources for unresolved signal
./md:error: error during elaboration
Note that the error is raised even if, as in our example, all drivers agree on the driving value.
