# vhdl D-Flip-Flops (DFF) and latches D-Flip-Flops (DFF)

## Example

In all examples:

• `clk` is the clock,
• `d` is the input,
• `q` is the output,
• `srst` is an active high synchronous reset,
• `srstn` is an active low synchronous reset,
• `arst` is an active high asynchronous reset,
• `arstn` is an active low asynchronous reset,
• `sset` is an active high synchronous set,
• `ssetn` is an active low synchronous set,
• `aset` is an active high asynchronous set,
• `asetn` is an active low asynchronous set

All signals are of type `ieee.std_logic_1164.std_ulogic`. The syntax used is the one that leads to correct synthesis results with all logic synthesizers. Please see the Clock edge detection example for a discussion about alternate syntax.

## Rising edge clock

``````process(clk)
begin
if rising_edge(clk) then
q <= d;
end if;
end process;
``````

## Falling edge clock

``````process(clk)
begin
if falling_edge(clk) then
q <= d;
end if;
end process;
``````

## Rising edge clock, synchronous active high reset

``````process(clk)
begin
if rising_edge(clk) then
if srst = '1' then
q <= '0';
else
q <= d;
end if;
end if;
end process;
``````

## Rising edge clock, asynchronous active high reset

``````process(clk, arst)
begin
if arst = '1' then
q <= '0';
elsif rising_edge(clk) then
q <= d;
end if;
end process;
``````

## Falling edge clock, asynchronous active low reset, synchronous active high set

``````process(clk, arstn)
begin
if arstn = '0' then
q <= '0';
elsif falling_edge(clk) then
if sset = '1' then
q <= '1';
else
q <= d;
end if;
end if;
end process;
``````

## Rising edge clock, asynchronous active high reset, asynchronous active low set

Note: set has higher priority than reset

``````process(clk, arst, asetn)
begin
if asetn = '0' then
q <= '1';
elsif arst = '1' then
q <= '0';
elsif rising_edge(clk) then
q <= d;
end if;
end process;
`````` PDF - Download vhdl for free