The short story
Whith VHDL 2008 and if the type of the clock is bit, boolean, ieee.std_logic_1164.std_ulogic or ieee.std_logic_1164.std_logic, a clock edge detection can be coded for rising edge
if rising_edge(clock) then
if clock'event and clock = '1' then -- type bit, std_ulogic or std_logic
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