verilog Synthesis vs Simulation mismatch Comparison
Example
wire d = 1'bx; // say from previous block. Will be 1 or 0 in hardware
if (d == 1'b) // false in simulation. May be true of false in hardware
wire d = 1'bx; // say from previous block. Will be 1 or 0 in hardware
if (d == 1'b) // false in simulation. May be true of false in hardware
