verilog Hello World


Example

The program outputs Hello World! to standard output.

module HELLO_WORLD(); // module doesn't have input or outputs
  initial begin
    $display("Hello World");
    $finish; // stop the simulator
  end
endmodule

Module is a basic building block in Verilog. It represent a collection of elements and is enclosed between module and end module keyword. Here hello_world is the top most (and the only) module .

Initial block executes at the start of simulation. The begin and end is used to mark the boundary of the initial block. $display outputs the message to the standard output. It inserts and end of line "\n" to the message.

This code can't by synthesized, i.e. it can't be put in a chip.