Intel x86 Assembly Language & Microarchitecture 32-bit registers


Example

When Intel produced the 80386, they upgraded from a 16-bit processor to a 32-bit one. 32-bit processing means two things: both the data being manipulated was 32-bit, and the memory addresses being accessed were 32-bit. To do this, but still remain compatible with their earlier processors, they introduced whole new modes for the processor. It was either in 16-bit mode or 32-bit mode - but you could override this mode on an instruction-by-instruction basis for either data, addressing, or both!

First of all, they had to define 32-bit registers. They did this by simply extending the existing eight from 16 bits to 32 bits and giving them "extended" names with an E prefix: EAX, EBX, ECX, EDX, ESI, EDI, EBP, and ESP. The lower 16 bits of these registers were the same as before, but the upper halves of the registers were available for 32-bit operations such as ADD and CMP. The upper halves were not separately accessible as they'd done with the 8-bit registers.

The processor had to have separate 16-bit and 32-bit modes because Intel used the same opcodes for many of the operations: CMP AX,DX in 16-bit mode and CMP EAX,EDX in 32-bit mode had exactly the same opcodes! This meant that the same code could NOT be run in either mode:

The opcode for "Move immediate into AX" is 0xB8, followed by two bytes of the immediate value: 0xB8 0x12 0x34

The opcode for "Move immediate into EAX" is 0xB8, followed by four bytes of the immediate value: 0xB8 0x12 0x34 0x56 0x78

So the assember has to know what mode the processor is in when executing the code, so that it knows to emit the correct number of bytes.